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Commit 92e63b59 authored by Allan Blanchard's avatar Allan Blanchard
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[wp] Compile logic infos even when not verifiable

parent 4c176ef4
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...@@ -396,6 +396,8 @@ class visitor = ...@@ -396,6 +396,8 @@ class visitor =
(* --- LOGIC INFO --- *) (* --- LOGIC INFO --- *)
| Dtype_annot(l,_)
| Dinvariant(l,_)
| Dfun_or_pred(l,_) -> | Dfun_or_pred(l,_) ->
begin begin
register_logic database self#section l ; register_logic database self#section l ;
...@@ -427,8 +429,6 @@ class visitor = ...@@ -427,8 +429,6 @@ class visitor =
(* --- OTHERS --- *) (* --- OTHERS --- *)
| Dvolatile _ | Dvolatile _
| Dinvariant _
| Dtype_annot _
| Dmodel_annot _ | Dmodel_annot _
| Dcustom_annot _ | Dcustom_annot _
| Dextended _ | Dextended _
......
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